By Ayman Fayed
This publication is dedicated to the topic of adaptive recommendations for clever analog and combined sign layout wherein totally sensible first-pass silicon is attainable. To our wisdom, this can be the 1st publication dedicated to this topic. The thoughts defined should still bring about quantum development in layout productiveness of advanced analog and combined sign platforms whereas considerably slicing the spiraling expenses of product improvement in rising nanometer applied sciences.
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Extra info for Adaptive Techniques for Mixed Signal System on Chip (The International Series in Engineering and Computer Science)
R. Jacob, Harry W. Li, David E. Boyce, “CMOS Circuit Design, Layout, and Simulation,” IEEE Press Series on Microelectronic Systems, New York, 1998. 3. Yuan Taur, Tak H. Ning, “Fundamentals Of Modern VLSI Devices,” Cambridge University Press, Cambridge 1998. 4. R. A. Blauschild, “An Integrated Time Reference,” ISSCC Dig. Tech. Papers, PP. 56-57, Feb. 1994. 5. Adel Sedra, Kenneth Smith “Microelectronic Circuits,” Third Edition, Saunders College Publishing, Toronto 1991. 6. K. Bult and G. J. G. M.
Since the cubic and higher-order terms are very small, they can be ignored, and only the square-term is used. Equation 3-8 will then be reduced to: ID ª V2 º K « VGS E1 VGS2 VT VDS DS » 2 ¼ ¬ (3-10) Using Eq. 3-10, Eqs. 3-1 through 3-7 for the circuit in Fig. 3-1 can be rewritten as: 3. Tunable Elements 43 I1 2 ª§ § · Vid · Vid · V2º § ¨ K « ¨VCM E1 ¨VCM VT ¸ VC C » ¸ ¸ ¸ 2 ¹ 2 ¹ 2 » © «¬¨© © ¹ ¼ (3-11) I2 2 ª§ § · Vid · Vid · V2º § ¨ K « ¨VCM E1 ¨VCM VT ¸ VC C » ¸ ¸ ¸ 2 ¹ 2 ¹ 2 » © «¬¨© © ¹ ¼ (3-12) I CM ª V2º 2 VT VC C » K « VCM E1 VCM 2 ¼ ¬ I O I CM I 2 ª§ V V ·V § K «¨¨ id E1 ¨ 2VCM id ¸ id 2 ¹ 2 © ¬© 2 · º ¸¸ VC » ¹ ¼ (3-14) I O I1 I CM ª§ V V ·V § K «¨¨ id E1 ¨ 2VCM id ¸ id 2 2 ¹ 2 © ¬© · º ¸¸ VC » ¹ ¼ (3-15) (3-13) Gm w I O wVid E ª1 º K « 2 E1VCM 1 Vid » VC 4 ¬2 ¼ (3-16) Gm w I O wVid E ª1 º K « 2 E1VCM 1 Vid » VC 2 4 ¬ ¼ (3-17) Equations 3-10 through 3-17 could now be used to provide a more accurate assessment of performance limitations in the circuit.
3-1 -10u -20u -30u IO- of the circuit in Fig. 3-2 IO+ of the circuit in Fig. 00 200m 400m 600m Differential Input (V) Figure 3-4. Output currents of transconductors in Fig. 3-1 and 3-2 at 100mV control voltage. 200u IO- of the circuit in Fig. 3-1 IO+ of the circuit in Fig. 3-1 Output Currents (A) 100u IO+ of the circuit in Fig. 3-2 IO- of the circuit in Fig. 00 IO- of the circuit in Fig. 3-1 IO+ of the circuit in Fig. 3-1 -100u IO- of the circuit in Fig. 3-2 IO+ of the circuit in Fig. 00 200m 400m 600m Differential Input (V) Figure 3-5.
Adaptive Techniques for Mixed Signal System on Chip (The International Series in Engineering and Computer Science) by Ayman Fayed